Tech Brief (May 26): Huawei Targets 1.4-Nanometer Chip Performance by 2031 With New Design Architecture

Huawei targets 1.4-nanometer chip performance by 2031

Huawei Technologies Co. Ltd. expects to match the performance of industry-leading 1.4-nanometer chips by 2031 using a novel design architecture, signaling a major step in bypassing U.S. curbs on its access to advanced manufacturing tools. He Tingbo, president of the company’s semiconductor division, unveiled the Tau (τ) Scaling Law at an international symposium on Monday. The new theoretical framework focuses on minimizing signal transmission time across vertically stacked chip layers rather than shrinking the physical size of transistors. Under the new approach, Huawei’s upcoming Kirin processors, due this autumn, will feature “LogicFolding” technology. By vertically stacking digital, analog, and memory circuits, the method shortens transmission paths and reduces resistance, allowing chips to operate more efficiently on older manufacturing nodes.