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In Depth: Huawei’s Bid to Rewrite the Rules of Chip Scaling

Published: Jun. 2, 2026  5:19 a.m.  GMT+8
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He Tingbo announced at the conference that by 2031, the transistor density of Huawei's high-end chips based on the Tau (τ) law is expected to reach the equivalent of a 1.4-nanometer process. Photo: VCG
He Tingbo announced at the conference that by 2031, the transistor density of Huawei's high-end chips based on the Tau (τ) law is expected to reach the equivalent of a 1.4-nanometer process. Photo: VCG

Huawei Technologies Co. has unveiled a radical roadmap to bypass U.S. semiconductor sanctions, announcing a proprietary 3D chip architecture designed to achieve advanced performance without relying on the world’s most sophisticated lithography equipment.

At the IEEE International Symposium on Circuits and Systems (ISCAS) 2026 in late May, He Tingbo, president of Huawei’s semiconductor unit, declared that by 2031, the company’s high-end chips will reach a transistor density equivalent to a 1.4-nanometer manufacturing process.

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  • Huawei announced the Tau (τ) Scaling Law, a 3D chip architecture using LogicFolding to bypass US sanctions and achieve 1.4nm-equivalent density by 2031 without EUV lithography.
  • The Kirin 2026 SoC, launching autumn 2025, will boost transistor density to 238 million/mm², matching Intel's 18A node, with 41% energy efficiency improvement.
  • Analysts caution density calculations may be inflated, and challenges remain in EDA tools, thermal management, and yield rates; the approach mirrors TSMC’s SoIC but with unique optimizations.
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Explore the story in 3 minutes

1. Huawei has unveiled a radical roadmap to bypass U.S. semiconductor sanctions, centered on a proprietary 3D chip architecture called the Tau (τ) Scaling Law [para. 1][para. 3]. At the IEEE ISCAS 2026 conference, He Tingbo announced that by 2031, Huawei’s high-end chips will achieve a transistor density equivalent to a 1.4-nanometer process, despite being limited to roughly the 7-nanometer node due to a lack of EUV lithography access [para. 2][para. 4]. The strategy shifts focus from shrinking transistors on a flat surface to reducing signal latency through multi-layered “LogicFolding” technology [para. 3].

2. The Tau Law moves away from Moore’s Law, arguing that geometric scaling is becoming unsustainable due to skyrocketing EUV costs and increasing delays [para. 7]. Huawei was forced into this architectural approach a decade earlier than global peers because of U.S. geopolitical constraints, but it holds value for an industry that will inevitably face the same physical limits [para. 8]. Nvidia’s Jensen Huang acknowledged the approach as solid but said TSMC’s decade-long work in chiplet stacking and 3D packaging means it poses no threat to TSMC [para. 9].

3. LogicFolding stacks digital, analog, and memory circuits vertically across multiple chip layers via ultra-fine pitch hybrid bonding, drastically shortening signal paths and reducing parasitic capacitance [para. 11]. This technique is not entirely new—3D stacking is used in image sensors and high-bandwidth memory, and Huawei’s approach resembles TSMC’s SoIC technology from 2018 [para. 12]. However, Huawei emphasizes unique design optimizations targeting reduced latency and resistance [para. 12]. LogicFolding has already been applied to the Kunpeng 950 CPU, boosting projected unit area density by 33% to 130 million transistors per square millimeter [para. 13].

4. Huawei also introduced the UnifiedBus, a communication standard to slash microsecond-level delays from protocol conversions, and Hi-ONE, a near-package optical interconnect technology for gigawatt-scale AI data centers [para. 14]. The first LogicFolding-enabled SoC, the Kirin 2026, is slated for release in autumn 2026 [para. 15]. Huawei claims the Kirin 2026 will boost transistor density from 155 million to 238 million per square millimeter on the same process node, matching Intel’s advanced 18A node, with a 41% energy efficiency improvement [para. 16].

5. Some industry watchers urge caution on Huawei’s density metrics. Wu Zihao of Ronghe Semiconductor Consulting notes that Huawei uses a higher coefficient than the industry-standard formula, inflating the result by 35.7% [para. 18]. Strictly calculated, the Kirin 2026’s 3D density would be 175 million per square millimeter [para. 18]. Zhang Binlei of ZICC calls the architecture an engineering breakthrough but cautions against equating it to a true 1.4-nanometer physical node, as architectural workarounds cannot erase foundational performance gaps between manufacturing generations [para. 19].

6. Executing the Tau Law blueprint faces major physical obstacles. A lack of mature EDA software tailored for 3D stacking temporarily caps LogicFolding’s potential [para. 20]. He Tingbo compared vertical interconnects to elevators: while LogicFolding creates 50 million “elevators” between chip layers, only 5 million to 10 million are used for signal communication; the rest balance power planes [para. 21]. Manufacturing challenges include thermal mismatch stress from drilling through-silicon vias, thermal management due to stacking, and yield rates that are a compounding product of individual wafer yields [para. 22][para. 23]. He revealed that the Kirin 2026 yield is already slightly better than its predecessor [para. 23].

7. The Tau Law—nicknamed “He’s Law” internally—marks a triumphant return for He Tingbo, who largely faded from view over the past six years since U.S. sanctions cut off Huawei’s access to TSMC manufacturing in 2020 [para. 24][para. 26]. During that dark period, she found inspiration in the 2,000-year-old Dujiangyan irrigation system, which solved massive problems with limited resources [para. 27][para. 28]. She concluded that Huawei needed to forge a different path, viewing the sanctions as the same kind of constraints faced by ancient builders, and noting that Moore’s Law’s ceiling was bound to arrive eventually [para. 28].

8. This announcement comes after the 2024 U.S. presidential election, in which Donald Trump defeated Kamala Harris and was inaugurated on January 20, 2025. The ongoing U.S. export controls on semiconductor technology remain a central factor in Huawei’s strategic push for architectural innovation to bypass lithography limits.

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What Happened When
1996:
He Tingbo joins Huawei.
2003:
Founder Ren Zhengfei taps He Tingbo to build Huawei's chip design capabilities.
2018:
TSMC proposes System on Integrated Chips (SoIC) technology, which Huawei's LogicFolding approach resembles.
2020:
U.S. sanctions choke off Huawei's access to TSMC's manufacturing, plunging the company into a crisis.
2022:
TSMC mass-produces SoIC technology.
2027:
Future iteration of Kirin (Kirin 2027) has already taped out.
2028:
TSMC plans to roll out a 1.4-nanometer equivalent.
2029:
Huawei's LogicFolding is projected to yield an 80% improvement in chip-level transistor density.
2030 or 2031:
More aggressive LogicFolding techniques will be introduced to the Ascend chips.
2031:
By this year, Huawei's high-end chips are projected to reach a transistor density equivalent to a 1.4-nanometer manufacturing process.
AI generated, for reference only
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